The present invention is directed to a charge pump circuit for providing relatively high voltage to a circuit on an integrated circuit from relatively low input voltage sources.
Charge pump circuits are well known in the prior art. Such circuits are used for generating voltages greater than those available at the power supply. On an integrated circuit chip such circuits are quite important where a particular circuit requires a voltage in excess of the Vdd voltage normally available to the chip. The erase circuit, for example, for nonvolatile memory often requires a voltage well in excess of Vdd because the Fowler-Nordheim tunneling process used for erasing the floating gate of such memory usually requires a relatively high voltage compared to Vdd.
In generating large on-chip voltages (i.e., in excess of twice Vdd) for use within standard CMOS processes (single n-well and single poly), solutions exist that individually address the reliability, efficiency and maximum-attainable voltage (i.e., the n-well/p-substrate reverse-bias breakdown voltage) issues for a specific implementation. No single solution is known, however, that simultaneously provides a good solution to all three of these issues. Typically the available circuitry is either highly efficient but provides a relatively low maximum attainable voltage or the circuitry is relatively inefficient but provides a relatively high maximum attainable voltage. New portable and wireless electronic products require both high efficiency (for extended battery powered operation) and high voltage.
In generating on-chip voltages larger than Vdd, charge is stored on capacitors, transferred through consecutive stages, providing a voltage at the final output stage, which is dependant upon the number of stages and the gain and efficiency of each stage. Two basic well-known approaches are the Dickson Voltage Multiplier circuit (Dickson, John F., xe2x80x9cOn-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Techniquexe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, June 1976, pp. 374-378) and the Voltage Tripler.
An example of the Dickson voltage multiplier circuit is illustrated in schematic form in FIG. 1. The two clock signals phi1 and phi2 are typically out of phase with one another and have amplitude Vphi as illustrated in FIG. 2 and the switches S1, S2, . . . , Sn-1 and Sn may be implemented with diodes or transistors. The multiplier operates by pumping packets of charge from stage to successive stage as the coupling capacitors C1, C2, . . . , Cn-1, Cn are successively charged and discharged during each half of the clock cycle. Because the voltages are allowed to grow from stage to stage, the average potentials at the end of each stage grow from input to output.
An example of the basic voltage tripler circuit is illustrated at FIG. 3. Using the same basic approach as the Dickson voltage multiplier circuit, each stage typically incorporates two capacitors, C1 and C2 and five switches, S1, S2, S3, S4 and S5. Switches S1, S2 and S3 are controlled by the clock signal phi2 while switches S4 and S5 are controlled by clock signal phi1 (the timing diagram of FIG. 2 works for this version as well). When Phi2 causes switches S1, S2 and S3 to close, C1 and C2 charge. When Phi2 opens switches S1, S2 and S3 and Phi1 closes switches S4 and S5 charge is passed along to the next stage.
The problems in creating voltages in excess of Vdd revolve around the efficiency, reliability and isolation provided by the xe2x80x9cswitchxe2x80x9d element used to transfer charge from stage to consecutive stage. FIG. 4A illustrates the configuration of a prior art charge-transfer switch in the form of a PMOS diode. FIG. 4B illustrates the configuration of a prior art charge-transfer switch in the form of a NMOS diode. This approach provides relatively good backwards isolation typical of diodes, however the fixed voltage drop Vd, also typical of diodes, reduces the voltage gain per stage.
Turning now to FIGS. 5A and 5B, implementations of MOS switches are illustrated schematically. FIG. 5A shows a PMOS switch under the control of clock signal xcfx861 (sometimes referred to herein as phi1) and FIG. 5B shows a NMOS switch under the control of clock signal xcfx862 (sometimes referred to herein as phi2). These switch elements have the advantage of a high gain per stage due to a lower voltage drop than is experienced with diodes, however they provide no voltage isolation beyond Vdd-Vd. In the case of a PMOS device, the lack of isolation comes from the fact that the well can be forward biased if the drain potential gets higher than the well potential. This case is reversed for an NMOS device within an n-well process as the well (substrate in this case) can only be forward biased if the drain potential is below that of the well/substrate. The NMOS within a single n-well process cannot be used for high-voltage generation because it cannot float (i.e., be isolated within its own well).
Accordingly, the present invention is directed to a voltage multiplier charge pump circuit for on-chip use, which exhibits efficiency and relatively high voltage output.
In accordance with a first aspect of the invention, a novel switch element includes (1) an NMOS transistor controlled by a first clock signal coupled between a first node and a first fixed voltage level, (2) a first PMOS well transistor controlled by a second clock signal (which may be a one shot type signalxe2x80x94a one-shot signal as used herein is a single pulse of short duration (compared to the clocking period) that is triggered by a clock edge) coupled between the first node and a voltage output node, and (3) a second PMOS well transistor controlled by the first node and coupled between a voltage input node and the voltage output node. The wells of both the first and second PMOS well transistors are coupled to the voltage output node to provide reverse isolation. In accordance with a second aspect of the present invention, a voltage multiplier circuit incorporates plural stages of the novel switch element to provide a multiplication of an input voltage. In accordance with a third aspect of the invention, a method of operation for the voltage multiplier circuit is provided.